DVCon India 2015

After its successful launch last year, the Design and Verification Conference & Exhibition India will be back in 2015! DVCon India provides an excellent platform to share knowledge, experience and best practices covering Electronic System Level Design & Verification for IP and SOC, VIP development and Virtual Prototyping for Embedded Software development and debug.
Sponsored by Accellera Systems Initiative, the conference provides multiple opportunities to interact with industry experts delivering keynote speeches, invited talks, tutorials, panel discussions, technical paper presentations, poster sessions and exhibits from ecosystem partners. The attendees will also get the latest information on various Accellera standards for system design, modelling and verification. These standards include UVM, SystemC (and its variants like SystemC-AMS, SCV, CCI, Synthesis subset), SystemVerilog, PSL, Assertions for AMS, Verilog, IP-XACT, OCP and many more.