Logic Breadboard Simulator

Logic Breadboard Simulator is a logic circuit simulator with breadboard and schematic editors, HDL input, virtual digital oscilloscope.
The breadboard has the following features.
Power connectors, two independent clock generators, scope with 32 channels.
Single touch hole and device selection. Wire to resistor,LED ,LED+resistor transformation. Device library. 7 step undo/redo. Custom circuits.
7 segment display.
ICs:
7400, 7401, 7402, 7403, 7404, 7405, 7406, 7407,7408, 7409, 7410, 7411, 7412, 7413, 7414, 7415, 7416, 7417, 7419, 7420, 7421, 7422, 7427, 7428, 7430, 7440, 7449
Currently available schematic components:
Transistors: NMOS, PMOS
Logic gates: buffer, inverter, and, nand, or, nor, exor, exnor, tri-state buffer and inverter
Flip flops: D latch, edge triggered D, JK flip flops, monostable
Multiplexers: 2 to 1, 4 to 1, 8 to 1.
Demultiplexers: 1 to 2, 1 to 4, 1 to 8
Indicators: LED, oscilloscope probe
Displays: decimal, hexadecimal
Switches: toggle button, push button
Constants: high and low.
The scheme editor comes from & logics app with some improvements.
Four times bigger canvas, faster router. Sub circuits on breadboard may have port labels.
Simply put an annotation to the circuit. The syntax is simple. Start with . and separate labels with dots. If the port is negated than start label with ~. The number of port labels must be equal to the number of ports.
E.g.
.B.C.~LT.~BI/RBO.~RBI.D.A.GND.e.d.c.b.a.g.f.Vcc
The place of the custom circuits is the "ics" directory.
Scheme editor features: custom subcircuit (black box), context sensitive menu, autorouter, 7 steps undo/redo, labels for far connections, automatic enlarge on selection, cloning, rotating, locked and unlocked move, vertical and horizontal alignment, move to center.
The digital circuit simulator works with three logic levels and three impedance values. They are low, undefined and high.
Wires optionally can display logic levels.
Switch level modelling, gate level modelling and complex device level modelling can be mixed in a circuit.
The simulator detects run time errors and puts error messages on the schematic.
Detected errors are:
Temporary short circuit conditions. When connected outputs have different or undefined levels and have low or undefined impedance.
Spike detection. When an input receives an impulse shorter than the configured value.
Flip flop setup, hold, recovery, resume time violations. Flip flops may enter a metastable state in these cases.
The virtual digital oscilloscope has the following current features: start, stop time, buffer length setting, time shift and zoom, up/down scroll, display of logical low, high, and undefined states.
The app contains HDL extension. It is possible to describe a circuit in a box using a very small subset of Verilog. The gates.s demo loads the following module from simple.v file:
module smpl_circuit (A,B,AND,NAND,OR,NOR,XOR,XNOR,BUF,NOT);
input A,B;
output AND,NAND,OR,NOR,XOR,XNOR,BUF,NOT;
and #10 g0(AND,A,B);
nand #10 g1(NAND,A,B);
or #10 g2(OR,A,B);
nor #10 g3(NOR,A,B);
xor #10 g4(XOR,A,B);
xnor #10 g5(XNOR,A,B);
buf #10 g6(BUF,A);
not #10 (NOT,A);
endmodule

and the test1.v file:
module circuit(A,B,C,y);
input A,B;
output y;
wire e;
and #30 g1(e,A,B);
or #30 g2(y,e,C);
endmodule
There is no runtime error detection inside the boxes.
Only the first compile time error is displayed.
The program comes with built in demo circuits. They help you to get started quickly.
See http://www.hexastyle.com/home/andlogics/first-3-steps for details.
You can easily simulate, analyse and modify operation and timing of the examples.
Built in examples:
74160, 74163 synchronous counter
74180 parity generator checker
74181 4 bit ALU
74147, 74148 priority encoder
transistor level modelling of CMOS gates
More examples can be downloaded from here:
http://www.hexastyle.com/home/andlogics/download-examples